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ralink: sync mt7621 pcie driver with latest SDK

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fixes newer ECO versions and a hang on reboot bug

Signed-off-by: John Crispin <blogic@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44008 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2015-01-17 14:50:59 +00:00
parent 7f8101ef57
commit ef97e25627
1 changed files with 19 additions and 25 deletions
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44
target/linux/ramips/patches-3.14/0016-MIPS-ralink-add-MT7621-pcie-driver.patch
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@ -12,7 +12,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/mips/pci/Makefile --- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1 @@ -41,6 +41,7 @@
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
@ -22,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
--- /dev/null --- /dev/null
+++ b/arch/mips/pci/pci-mt7621.c +++ b/arch/mips/pci/pci-mt7621.c
@@ -0,0 +1,797 @@ @@ -0,0 +1,791 @@
+/************************************************************************** +/**************************************************************************
+ * + *
+ * BRIEF MODULE DESCRIPTION + * BRIEF MODULE DESCRIPTION
@ -597,11 +597,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#if defined (CONFIG_PCIE_PORT2) +#if defined (CONFIG_PCIE_PORT2)
+ val |= RALINK_PCIE2_RST; + val |= RALINK_PCIE2_RST;
+#endif +#endif
+ DEASSERT_SYSRST_PCIE(val);
+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
+
+ bypass_pipe_rst();
+ set_phy_for_ssc();
+ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST); + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
+ printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
+#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/ +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
@ -627,24 +622,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#endif +#endif
+ DEASSERT_SYSRST_PCIE(val); + DEASSERT_SYSRST_PCIE(val);
+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
+#if defined (CONFIG_PCIE_PORT0) +
+ read_config(0, 0, 0, 0x70c, &val); + if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
+ val &= ~(0xff)<<8; + bypass_pipe_rst();
+ val |= 0x50<<8; + set_phy_for_ssc();
+ write_config(0, 0, 0, 0x70c, val); + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
+#endif
+#if defined (CONFIG_PCIE_PORT1)
+ read_config(0, 1, 0, 0x70c, &val);
+ val &= ~(0xff)<<8;
+ val |= 0x50<<8;
+ write_config(0, 1, 0, 0x70c, val);
+#endif
+#if defined (CONFIG_PCIE_PORT2)
+ read_config(0, 2, 0, 0x70c, &val);
+ val &= ~(0xff)<<8;
+ val |= 0x50<<8;
+ write_config(0, 2, 0, 0x70c, val);
+#endif
+ +
+#if defined (CONFIG_PCIE_PORT0) +#if defined (CONFIG_PCIE_PORT0)
+ read_config(0, 0, 0, 0x70c, &val); + read_config(0, 0, 0, 0x70c, &val);
@ -799,16 +781,28 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ read_config(0, 2, 0, 0x4, &val); + read_config(0, 2, 0, 0x4, &val);
+ write_config(0, 2, 0, 0x4, val|0x4); + write_config(0, 2, 0, 0x4, val|0x4);
+ // write_config(0, 1, 0, 0x4, val|0x7); + // write_config(0, 1, 0, 0x4, val|0x7);
+ read_config(0, 2, 0, 0x70c, &val);
+ val &= ~(0xff)<<8;
+ val |= 0x50<<8;
+ write_config(0, 2, 0, 0x70c, val);
+ case 3: + case 3:
+ case 5: + case 5:
+ case 6: + case 6:
+ read_config(0, 1, 0, 0x4, &val); + read_config(0, 1, 0, 0x4, &val);
+ write_config(0, 1, 0, 0x4, val|0x4); + write_config(0, 1, 0, 0x4, val|0x4);
+ // write_config(0, 1, 0, 0x4, val|0x7); + // write_config(0, 1, 0, 0x4, val|0x7);
+ read_config(0, 1, 0, 0x70c, &val);
+ val &= ~(0xff)<<8;
+ val |= 0x50<<8;
+ write_config(0, 1, 0, 0x70c, val);
+ default: + default:
+ read_config(0, 0, 0, 0x4, &val); + read_config(0, 0, 0, 0x4, &val);
+ write_config(0, 0, 0, 0x4, val|0x4); //bus master enable + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
+ // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
+ read_config(0, 0, 0, 0x70c, &val);
+ val &= ~(0xff)<<8;
+ val |= 0x50<<8;
+ write_config(0, 0, 0, 0x70c, val);
+ } + }
+ register_pci_controller(&rt2880_controller); + register_pci_controller(&rt2880_controller);
+ return 0; + return 0;